Reduction of Parasitic Capacitance in Indium‐Gallium‐Zinc Oxide (a‐IGZO) Thin‐Film Transistors (TFTs) without Scarifying Drain Currents by Using Stripe‐Patterned Source/Drain Electrodes

Suhui Lee; Yuanfeng Chen; Jaekwon Jeon; Chanju Park; Jin Jang

Index: 10.1002/aelm.201700550

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Abstract

A new device structure of oxide thin‐film transistor (TFT) having lower overlap capacitance without scarifying the drain current is proposed. This can be used for high‐speed circuits and high frame rate displays using the conventional TFT manufacturing process. The existence of spreading currents in amorphous indium‐gallium‐zinc oxide (a‐IGZO) TFTs with stripe‐patterned source/drain (S/D) electrodes is demonstrated. The device performances of the a‐IGZO TFTs with various widths of stripe‐patterned S/D electrodes and open spaces between them are compared. The drain currents of the a‐IGZO TFTs are almost same when the width of open space changes from 0 to 10 µm because of the existence of spreading currents. The overlap capacitance between gate and S/D of the a‐IGZO TFTs can be significantly reduced without scarifying drain currents by using stripe‐patterned S/D electrodes. The operation frequency of the ring oscillator made of the TFTs with stripe S/D electrodes with 10 µm open space width is 2.5 times that made of the conventional a‐IGZO TFTs. This spreading current concept can be widely used for the design of oxide TFT array with low RC (resistance capacitance product) delay for high‐speed circuits.